Tutorial #2: Digilent Spartan 3E + Xilinx ISE + Verilog

Product Category: All

Family: Spartan3E

Device: XC3S500E

Package: FG320

Speed: -4

------- Verilog File -------

[ and_gate.v ]

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:54:18 01/20/2011
// Design Name:
// Module Name: and_gate
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module and_gate(
input a,
input b,
output c
);

assign c = a & b;

endmodule

[ and_gate_cf.ucf ]

# switch 0
NET "a" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;

# switch 1
NET "b" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;

# led 0
NET "c" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;

ISE v.12.2

last update: January 20, 2011